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      2. 高級硬件工程師英文簡歷表格

        時間:2024-09-03 18:50:05 英文簡歷表格 我要投稿
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        高級硬件工程師英文簡歷表格

          在編寫個人簡歷之前需要目標企業(yè)進行調(diào)查了解,首先要知道的信息就是企業(yè)招聘的職位有哪些。一些大企業(yè)招聘通常會只有一個職位、崗位,求職者編寫個人簡歷要有針對的目標,其目標職位要是在招聘的職位范圍內(nèi)。

        高級硬件工程師英文簡歷表格

          企業(yè)中的職務(wù)有好很多,能提供給求職者的崗位要根據(jù)其個人專業(yè)以及才能而來,不同的職務(wù)責任不同、工作任務(wù)不同,在編寫個人簡歷之前要知道你所應(yīng)聘的職位是做什么工作的,針對這樣的工作你具有怎樣的優(yōu)勢。同時,還需要了解該職務(wù)招聘的條件要求,諸如對學歷的要求、對專業(yè)的要求,還有對技能的要求等等。

          最后在職人員在對目標企業(yè)的信息了解上,還應(yīng)該包括有企業(yè)的文化特點以及企業(yè)產(chǎn)品,企業(yè)的文化特點關(guān)系對方篩選簡歷的風格,還有所欣賞人才的類型。企業(yè)產(chǎn)品信息在求職簡歷中同樣可作為一個參考的材料,畢竟以后的工作都是圍繞產(chǎn)品展開。

        Name: yjbys Hukou:Shanghai
        Residency:Shanghai Work Experience: 
        Current Salary:  Tel: 
        E-mail:www.ruiwen.com/jianli
        Career Objective
        Desired Industry: Electronics/Semiconductor/IC ,Science/Research ,Government ,Others ,Testing, Certification
        Desired Position: Senior Hardware Engineer ,Semiconductor Technology, Branch Office Manager ,Chief Representative ,Research Specialist Staff
        Desired address: Shanghai ,Hongkong ,Beijing ,Taiwan ,Macao Desired Salary: Negotiable
         Work Experience
        20xx/06—Present ***Company
          Industry: Electronics/Semiconductor/IC
        Intel Flash Engineering Department Individual Contributor
        Responsibilities:
        I have been working in Intel Flash Assembly & Test Engineering
        Department as an Individual Contributor since June of 20xx.
        Being Leader of ATE Yield team, I have been working with the team members to improve the products yield. Our efforts are paid off:
        1. The yield of year 20xx has been dramatically increased than that of year 20xx.
        2. The yield of all products, consecutively meets the goal.
        3. The total amount of cost saving due to yield improvement is more than $1 million compared with year 20xx. Being the Leader of Board Repair Team in ATE, I worked with my team members, setup a set of new procedure to replace the current one, I defined the schedule, divided the roles & responsibilities among team members, follow up the progress. Finally, the team has made a great cost saving of $2.5M in 20xx.
        Report Directly to: Department ManagerNumber of Subordinate: 14
        Reference: Bao Powel
        Achievements: Being Leader of ATE Yield team, I have been working with the team members to improve the products yield.
        Our efforts are paid off:
        1. The yield of year 20xx has been dramatically increased than that of year 20xx.
        2. The yield of all products, consecutively meets the goal.
        3. The total amount of cost saving due to yield improvement is more than $1 million compared with year 20xx. Being the Leader of Board Repair Team in ATE, I worked with my team members, setup a set of new procedure to replace the current one, I defined the schedule, divided the roles & responsibilities among team members, follow up the progress. Finally, the team has made a great cost saving of $2.5M in 20xx.
        20xx/01—20xx/05 Intel(Shanghai) Technology Development Ltd. Company
          Industry: Electronics/Semiconductor/IC
        Intel STTD-China Department Electronics Development Engineer
        Responsibilities:
        1. I had been working in STTD-China since Jan 20xx to May 20xx as a senior module engineer.
        2. At that time, as a main contributor of this project, we succeeded in developing a set of MASSIVELY PARALLEL CLASS TEST equipment, which is able to test more than 6700 units in one time.
        Report Directly to: Hopman Mark   Number of Subordinate: 14
        Reference: Bao Powel
        Reason for Leaving: I was transferred to Intel(Shanghai)Products Ltd. Company due to the internal re-organization in June of 20xx.
        Achievements: As a main contributor of STTD-China department, I co-work with my colleagues to succeed in developing a set of MASSIVELY PARALLEL CLASS TEST equipment, which is able to test more than 6700 units in one cycle.
        20xx/05—20xx/01 Nanyang University of Science & Technology
          Industry: Electronics/Semiconductor/IC
        Electronics & Electrical Engineering Department Research Fellow
        Responsibilities:
        1. I work in Electronics & Electrical Engineering Department of Nanyang University of Science & Technology as a Research Fellow.
        2. I majored at Gate Oxide Reliability Research in the duration.
        Report Directly to: Professor Pey Kin Leoh 
        Subordinate: 3
        Reference: Patrick Low
        Reason for Leaving: I completed the project which I undertook by myself, and want to do more challenging job.
        Achievements: In less than one year, I made a lot of experiments and acquired the wonderful data for the project by myself.
        Project Experience
        20xx/01—Present Assembly NPI (New Product Introduction)
          Project Description: To introduce more products into Intel Flash Assembly factory, I join Assembly NPI team and work as the team leader. I coordinate with IE, Planner, Marketing guy and Engineer to select new product items, do demo in factory, and then qualify it.
        Responsibility: I am working as NPI Team leader and coordinate all team members, define the NPI candidate, make Assembly build plan, follow up the progress.
        20xx/01—20xx/12 Marginal Electrical Boards Rescue
          Project Description: To rescue some electrical boards of testing equipment, a Task Force team was built up and led by me. We categorized each kind of board, made historical failure analysis on each kind of board and around &2.5 million dollars was saved finally.
        Responsibility: Being the team leader, I took the job of data analysis, define each member's role, make program plan, coordinate each team member and follow up the progress.
        20xx/10—20xx/05 Optimization the current Test Process Order for Flash Memory
          Project Description: To simplify the current Test procedure and enhance the working efficiency, a Task Force team has been called and started by me.
        Responsibility: Being the Project leader, I take the main responsibility, such as, design, plan, organize and implement.
        20xx/05—20xx/12 Test Yield of Flash memory Improvement
          Project Description: To improve the test yield of different products, a Task Force team was built up and led by me. Being the team leader, I worked with all team members to dig out the failure root cause for each product, defined action taken plan for each emergency case, coordinated each team member and make pro-active plan to avoided unexpected things happen.
        Responsibility: Being the team leader of Improving Test Yield, coordinate each team member, make program plan and follow up.
        Education and Training
        20xx/05—20xx/01 Nanyang University of Science & Technology Microelectronics Doctorate
          I worked in Nan yang University of Science & Technology as a Research Fellow. I major at Gate oxide Reliability research in the duration.
        20xx/03—20xx/03 Seoul National University of Korea Microelectronics Others
          I had been working in National Physical Lab of Seoul National University in Korea since March of 20xx to March of 20xx as a Post-doctor. Where I unhook the project of research & development of Carbon-Nan tube Biosensor. And only after one year, an EIS sensor based on CMOS technology has been successfully produced. And one SCI paper about it has been published in Semiconductor Science and Technology.
        20xx/03—20xx/03 Shanghai Institute of Microsystems and Information Technology,Chinese Academy of Sciences Information Technology Doctorate
        20xx/09—20xx/03 Nanjing University of Science & Technology Material Science and Engineering Master
          Being a master student of this period, I have published one EI paper about Super-fine metal power's electrical characteristics.
        20xx/09—20xx/07 Nanjing University of Science & Technology Material Science and Engineering Bachelor
        20xx/07—20xx/07 Assistant Engineer in Quality Verification Department, Boiler Factory in Zhengzhou city of Henan resistant Engineer in Quality Verification Department
        Professional Skills
        Language Skills: English: EXCELLENT
        Korean: AVERAGE
        Computer Skills: Technology   skilled 96Month
        SAP   understanding 8Month
        Certificate: 20xx/11  MCSE
        20xx/06  CET6
        Self-appraisal
        7 years working experience of Semiconductor Industry and where 2 years overseas working/study experience. Smart working, innovation thinking and very talented creative working model.

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